Technically speaking it's a clock divider, specifically it that generates the horizontal and vertical video timing signals divided from the master clock.I made my own implementation with simple thru-hole TTL gates :
I succesfully tested my design on a Galaga PCB :
This open the way to a future implementation of this custom IC onto a CPLD or FPGA (already done by someone else though).
I think I am in the market to purchase some of these repro customs!
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